The present invention relates to a ferroelectric capacitor, a semiconductor memory device employing the ferroelectric capacitor, and fabrication methods for the capacitor and memory device.
One application of the invention is in ferroelectric random-access memory (FeRAM), a type of non-volatile memory featuring high write endurance and low power consumption. Already employed in electronic devices requiring this combination of features, FeRAM is viewed as a promising future replacement for present static, dynamic, and flash memory devices.
A typical FeRAM memory cell comprises a switching transistor and a ferroelectric capacitor. The ferroelectric capacitor may be stacked over the transistor, or disposed to one side in a planar arrangement. The ferroelectric capacitor comprises a ferroelectric body disposed between two electrodes. In the conventional fabrication process, the ferroelectric material and electrode material are patterned by etching.
A problem encountered in the fabrication of conventional ferroelectric memory devices is that etching disrupts the crystal structure of the ferroelectric material and introduces unwanted impurities. This type of damage is caused both when the ferroelectric material itself is etched, and when an underlying layer such as the bottom electrode layer is etched. To repair the damage, the device must be repeatedly annealed during the fabrication process, but this repeated annealing tends to alter transistor characteristics, leading to a memory device that does not perform as designed.
The damage caused during the etching of underlying layers can be avoided by using an etching mask to protect the ferroelectric layer, so that it is not exposed to the etching plasma, but this increases the cost of the fabrication process.
The damage caused by etching of the ferroelectric material itself cannot be avoided in this way. Moreover, typical ferroelectric materials, such as bismuth strontium titanate (BST) and lead zirconium titanate (PZT), must be heated to a high temperature to form the desired crystalline structure, and must be annealed at an equally high temperature to repair damage to the crystalline structure. In particular, BST, which has the advantage of a longer lifetime than PZT, must be heated to a temperature of at least seven hundred fifty degrees Celsius (750xc2x0 C.). Repeated annealing at this high a temperature can markedly alter transistor characteristics.
In a ferroelectric memory device with a stacked-capacitor structure, the bottom electrode is often made of platinum, which has an undesirable tendency to react with the polysilicon plug coupling the bottom electrode to the switching transistor. This unwanted reaction can be suppressed by providing an intervening barrier film of titanium or titanium nitride. Under repeated high-temperature annealing, however, the unwanted reaction may take place despite the barrier film. As a result, platinum-polysilicon electrical continuity is degraded.
A further problem caused by etching, particularly by dry etching, is that it creates a ferroelectric capacitor with sloping sides, which wastes space and limits integration density. A still further problem caused by dry etching and other techniques that are employed, such as ion milling, is that the damage they cause to the edges of the ferroelectric body in the capacitor can lead to badly misshapen capacitor configurations, particularly in highly integrated memory devices with small dimensions.
It is accordingly an object of the present invention to protect the ferroelectric material in a ferroelectric capacitor from etching damage.
Another object of the invention is to-increase the integration density of a memory device employing ferroelectric capacitors.
Another object is to simplify the fabrication of a memory device employing ferroelectric capacitors.
The invented capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top electrode and the bottom electrode, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body.
The invention also provides a fabrication process for the invented capacitor, comprising the steps of:
(a) forming a bottom electrode film on a substrate;
(b) forming a dielectric film on the bottom electrode film;
(c) creating a hole in the dielectric film;
(d) forming a ferroelectric film covering the dielectric film and filling the hole;
(e) removing the ferroelectric film from above the dielectric film, leaving a ferroelectric body in the hole;
(f) forming a top electrode film covering the dielectric film and ferroelectric body;
(g) patterning the top electrode film to form the top electrode;
(h) patterning the first dielectric film to form the dielectric lining; and
(i) patterning the bottom electrode film to form the bottom electrode.
Step (e) is preferably performed by chemical-mechanical polishing, thereby avoiding etching damage to the ferroelectric body.
Steps (g), (h), and (i) may be carried out with a single mask, the shape of which is transferred to the top electrode, dielectric lining, and bottom electrode. A compact capacitor with straight sides, aligned perpendicular to the substrate, is thereby created. This capacitor is particularly suitable for high-density integration.
The invention also provides a planar memory element incorporating the invented capacitor, and a process for fabricating the planar memory element.
The invention furthermore provides a stacked memory element incorporating the invented capacitor, and a process for fabricating the stacked memory element. In the stacked memory element, the capacitor is disposed above a transistor, separated from the transistor by an interlayer dielectric film. The bottom electrode of the capacitor is electrically coupled to an electrode of the transistor by a conductor disposed in a contact hole in the interlayer dielectric film. A barrier layer may be provided between the bottom electrode and the conductor, to prevent unwanted chemical reactions. The barrier layer may be surrounded by another dielectric film and may be formed by chemical-mechanical polishing.
Fabrication of the invented memory elements is simplified in that the ferroelectric body in the capacitor is protected from etching damage, so repeated annealing to repair such damage is not necessary.
Forming the barrier layer in a stacked memory element by chemical-mechanical polishing instead of etching also simplifies the fabrication process, when the barrier layer comprises a material that is difficult to etch.